This invention relates to a digital-to-analog converter for converting a digital signal having a word length n into an analog signal, comprising
a series arrangement of a first and a second integrating circuit each having an input and an output and a control signal input, the output of the first integrating circuit being coupled to the input of the second integrating circuit,
a control unit for supplying a first and a second control signal at a first and a second output, respectively, coupled to the control signal input of the first and the second integrating circuit, respectively, for applying the first and the second control signal to the first and the second integrating circuit, respectively,
the first and the second integrating circuit being adapted to perform an integration step under the influence of the first and the second control signal and the control unit being adapted to generate, in this order, the first control signal M1 times, the second control signal M2 times, the first control signal M3 times and the second control signal M4 times.
A digital-to-analog converter to this type is known from the published Japanese Patent Application (kokai) No. 59-8427 and is intended to convert an n-bit digital signal into an analog signal. The integrating circuits in the known converter are in the form of analog integrators. However, it is alternatively possible to form the integrating circuits as (analog) summation devices, charge-coupled devices (CCDs) or switched capacitor integrators.
The known converter is intended to convert 16-bit digital signals into analog signals and it operates as follows. In the first integrating circuit a first value is derived under the influence of M1 times the first control signal, which value is proportional to 2.sup.8 Vref, in which Vref is a reference value. Subsequently, an analog signal is derived in the second integrating circuit under the influence of M2 times the second control signal, which analog signal is proportional to MSB.2.sup.8 Vref, in which MSB is equal to the value of the binary number of the eight most significant bits of the 16-bit digital signal. Subsequently the output of the first integrating circuit is brought to an initial level (reset to zero in this case) under the influence of a reset signal of the control unit. Subsequently a second value is derived in the first integrating circuit under the influence of M3 times the first control signal, which value is proportional to Vref. Then an analog signal is derived in the second integrating circuit under the influence of M4 times the second control signal, which analog signal is proportional to MSB.2.sup.8 Vref+LSB.Vref, in which LSB is equal to the value of the binary number of the eight least significant bits of the 16-bit digital signal. The known converter appears to have a disturbing offset component in the analog output signal.